The TS5 Master Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The TS5 Master Controller IIP can be implemented in any technology.
The Master Controller IIP core supports the JEDEC TS5111, TS5110 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, Wishbone, Avalon, PLB, Tilelink, Wishbone or custom buses.
The Master Controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Master Controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
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