LPDDR3

The LPDDR3 Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The LPDDR3 Controller IIP can be implemented in any technology.

The LPDDR3 Controller IIP core supports the LPDDR3 protocol standard of JESD209-3, JESD209-3B and JESD209-3C specification and is compatible with DFI-version 3.1 or higher specification Compliant. LPDDR3 Controller IIP also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

The LPDDR3 Controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The LPDDR3 Controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.