The SDIO Device IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The SDIO Device IIP can be implemented in any technology.
The SDIO Device IIP core supports the Part 1 Physical Layer Specification Version 3.01 and SD specification Part E1 SDIO version 3.00. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, Wishbone, VCI, Avalon PLB, Wishbone or custom buses.
The SDIO Device IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The SDIO Device IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
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