The DMA Controller is full featured, easy-to-use, synthesizable design that can be used with any SOC bus protocol based systems as a controller to transfer data directly from system memory to IP core or from IP core to system memory.
The DMA Controller IIP core supports multiple channels. Through its compatibility, it provides a simple interface to any IP core with the appropriate logic in between. The DMA Controller IIP can be implemented in any technology.
The DMA Controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The DMA Controller IIP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation. SOC master and SOC Slave Interface supports AXI/AHB/APB/OCP/Tilelink/Avalon/VCI/Wishbone protocols.
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