The SAE J2716 Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The SAE J2716 Controller IIP can be implemented in any technology.
The SAE J2716 Controller IIP core supports the SENT specification SAE J2716 APR2016. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The SAE J2716 Controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The SAE J2716 Controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
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