The CXL Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The CXL Controller IIP can be implemented in any technology.
The CXL Controller IIP core supports the CXL 1.0 and 1.1 Specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture – AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
The CXL Controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The CXL Controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
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