The SATA Host Controller IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The SATA Host Controller IP can be implemented in any technology.
The SATA Host Controller IP core supports the SATA version 3.5 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, VCI, Avalon PLB, Wishbone or custom buses.
The SATA Host Controller IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The SATA Host Controller IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
0755-8671 9961