The VDC-M Decoder IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The VDC-M Decoder IIP can be implemented in any technology.
The VDC-M Decoder IIP core supports the VESA Display Stream Compression-M (VDC-M) version 1.1 and 1.2 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The VDC-M Decoder IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The VDC-M Decoder IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation
0755-8671 9961