The SPDIF IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SOC or FPGA development. The SPDIF IIP can be implemented in any technology.
The SPDIF IIP core supports the SPDIF 2.2A standard. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, Wishbone, VCI, Avalon PLB, Tilelink or custom buses.
The SPDIF IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The SPDIF IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
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