Watchdog Timer

The Watchdog IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SOC or FPGA development. The Watchdog IIP can be implemented in any technology.

The Watchdog IIP core supports the standard protocol of Watchdog. Watchdog IIP supports a variety of host bus interfaces for easy adoption into any design architecture – AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

The Watchdog IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Watchdog IIP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.