The Virtual GPIO Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The Virtual GPIO IIP can be implemented in any technology.
The Virtual GPIO IIP core supports the standard protocol of MIPI Virtual GPIO specifications. Virtual GPIO IIP also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, AXI, Wishbone, VCI, Avalon, PLB, Wishbone or custom buses.
The Virtual GPIO IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Virtual GPIO IIP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
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