The UART controller IP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The UART controller IP can be implemented in any technology.
The UART controller IP core supports the standard UART specifications. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The UART IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The UART IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
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